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dc.contributor.authorSchielke, Philip
dc.date.accessioned 2017-08-02T22:03:44Z
dc.date.available 2017-08-02T22:03:44Z
dc.date.issued 1998-09-15
dc.identifier.urihttps://hdl.handle.net/1911/96498
dc.description.abstract Instruction scheduling is a code reordering transformation that attempts to hide latencies present in modern day microprocessors. Current applications of these microprocessors and the microprocessors themselves present new parameters under which the scheduler must operate. For example, some multiple functional unit processors have partitioned register sets. In some applications, increasing the static size of a program may not be an acceptable tradeoff for gaining improved running time. The interaction between the scheduler and the register allocator can also dramatically affect the performance of the compiled code. In this work we will look at global scheduling techniques that do not replicate code, including scheduling overextended basic blocks. We also look at a replacement to the traditional list scheduler based on the techniques of iterative repair. Finally, we explore the interaction between instruction scheduling and register allocation, and look at ways of combining the two problems.
dc.format.extent 27 pp
dc.language.iso eng
dc.rights You are granted permission for the noncommercial reproduction, distribution, display, and performance of this technical report in any format, but this permission is only for a period of forty-five (45) days from the most recent time that you verified that this technical report is still available from the Computer Science Department of Rice University under terms that include this permission. All other rights are reserved by the author(s).
dc.title Issues in Instruction Scheduling
dc.type Technical report
dc.date.note September 15, 1998
dc.identifier.digital TR98-323
dc.type.dcmi Text
dc.identifier.citation Schielke, Philip. "Issues in Instruction Scheduling." (1998) https://hdl.handle.net/1911/96498.


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