Improving TLB Miss Handling with Page Table Pointer Caches
Wu, Michael; Zwaenepoel, Willy
DateDecember 16, 1997
Page table pointer caches are a hardware supplement for TLBs that cache pointers to pages of page table entries rather than page table entries themselves. A PTPC traps and handles most TLB misses in hardware with low overhead (usually a single memory access). PTPC misses are filled in software, allowing for an easy hardware implementation, similar in structure to a TLB. Since each PTPC entry refers to an entire page of page table entries, even a small PTPC maps a large amount of address space and achieves a very high hit rate. The primary goal of a PTPC is to lower TLB miss handling penalties. The combination of a TLB with a small PTPC provides good performance even in situations where standard TLBs alone perform badly (large workloads or multimedia applications). The advantage of this design is that we can continue to use small fixed size pages with standard TLBs. Since PTPCs use traditional page table structures and page sizes, they are very simple to implement in hardware and require minimal operating system modifications. Our simulations show that the addition of a PTPC to a system with a TLB can reduce miss handling costs by nearly an order of magnitude. Small PTPCs are extremely effective and the combination of small to medium sized TLBs coupled with smallPTPCs are an efficient alternative to large TLBs.