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dc.contributor.authorDevadas, Srinivas
Kharaya, Akshat
Koushanfar, Farinaz
Majzoobi, Mehrdad
dc.date.accessioned 2017-08-02T22:03:15Z
dc.date.available 2017-08-02T22:03:15Z
dc.date.issued 2014-08-18
dc.identifier.urihttps://hdl.handle.net/1911/96414
dc.description.abstract This paper proposes a novel approach for automated implementation of an arbiter-based physical unclonable function (PUF) on field programmable gate arrays (FPGAs). We introduce a high resolution programmable delay logic (PDL) that is implemented by harnessing the FPGA lookup-table (LUT) internal structure. PDL allows automatic fine tuning of delays that can mitigate the timing skews caused by asymmetries in interconnect routing and systematic variations. To thwart the arbiter metastability problem, we present and analyze methods for majority voting of responses. A method to classify and group challenges into different robustness sets is introduced that enhances the corresponding responses’ stability in the face of operational variations. The trade-off between response stability and response entropy (uniqueness) is investigated through comprehensive measurements. We exploit the correlation between the impact of temperature and power supply on responses and perform less costly power measurements to predict the temperature impact on PUF. The measurements are performed on 12 identical Virtex 5 FPGAs across 9 different accurately controlled operating temperature and voltage supply points. A database of challenge response pairs (CRPs) are collected and made openly available for the research community.
dc.format.extent 19 pp
dc.language.iso eng
dc.rights You are granted permission for the noncommercial reproduction, distribution, display, and performance of this technical report in any format, but this permission is only for a period of forty-five (45) days from the most recent time that you verified that this technical report is still available from the Computer Science Department of Rice University under terms that include this permission. All other rights are reserved by the author(s).
dc.title Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines
dc.type Technical report
dc.date.note August 18, 2014
dc.identifier.digital TR14-03
dc.type.dcmi Text
dc.identifier.citation Devadas, Srinivas, Kharaya, Akshat, Koushanfar, Farinaz, et al.. "Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines." (2014) https://hdl.handle.net/1911/96414.


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