Efficient Characterization of Processor Memory Hierarchies
Master of Science
A processor’s memory hierarchy has a major impact on the performance of running code. As memory hierarchies have become deeper and more complex, it has become more difficult to find specific, detailed information on those hierarchies. The academic community has a history of developing techniques to measure some of those parameters; experience suggests that hardware features such as prefetch engines would lead the older techniques to produce inaccurate results. To make matters more complex, the use of shared structures in the memory hierarchy in multicore processors introduces uncertainty into the notion of capacity in shared caches and TLBs, while the proliferation of distinct processor models creates a multitude of machines with different capacities in the upper levels of the hierarchy. To address these challenges, we have developed a suite of portable tools that efficiently derive many of the effective parameters of processor memory hierarchies in at most a few seconds. We also present a robust automatic approach to analyze the results and an experimental validation on a collection of processors.
Efficient Characterization; Automatic Analysis; Memory Hierarchies; Cache and TLB Test