Now showing items 98-117 of 245

    • Garbage Collector Memory Accounting in Language-Based Systems 

      Price, David W.; Rudys, Algis; Wallach, Dan S. (2003-11-11)
      Language run-time systems are often called upon to safely execute mutually distrustful tasks within the same runtime, protecting them from other tasks' bugs or otherwise hostile behavior. well-studied access controls exist in systems such as Java to prevent unauthorized reading or writing of data, but techniques to measure and control resource usage ...
    • Gleaning Network-Wide Congestion Information from Packet Markings 

      Dinu, Florin; Ng, T. S. Eugene (2010-06-29)
      Distributed control protocols routinely have to operate oblivious of dynamic network information for scalability or complexity reasons. However, more informed protocols are likely to make more intelligent decisions. We argue that protocols can leverage dynamic congestion information without suffering the mentioned penalties. In this paper we show ...
    • Gradual Typing: Isabelle/Isar Formalization 

      Siek, Jeremy; Taha, Walid (2006-04-07)
      This report formalizes a gradual type system using the Isabelle/Isar proof language and proof assistant. Gradual typing combines static typing and dynamic typing in the same language, allowing a programmer to gradual migrate portions of a program between the two typing disciplines.
    • Hack-a-Vote: Demonstrating Security Issues with Electronic Voting Systems 

      Bannet, Jonathan; Price, David W.; Rudys, Algis; Singer, Justin; Wallach, Dan S. (2003-11-21)
      A representative democracy depends on a universally trusted voting system for the election of representatives; voters need to believe that their votes count, and all parties need to be convinced that the winner and loser of the election were declared legitimately. Direct recording electronic (DRE)voting systems are increasingly being deployed to fill ...
    • Hierarchical Attribute Grammars: Dialects, Applications and Evaluation Algorithms 

      Carle, Alan (1992-05)
      Although attribute grammars have been applied successfully to the specification of many different phases of analysis and transformation of complex language processing systems, including type checking, data flow analysis, constant propagation and dead code elimination, little success has been achieved in applying attribute grammars to the specification ...
    • How Much Do Unstated Problem Constraints Limit Deep Robotic Reinforcement Learning? 

      Lewis, W. Cannon II; Moll, Mark; Kavraki, Lydia E. (2019)
      Deep Reinforcement Learning is a promising paradigm for robotic control which has been shown to be capable of learning policies for high-dimensional, continuous control of unmodeled systems. However, Robotic Reinforcement Learning currently lacks clearly defined benchmark tasks, which makes it difficult for researchers to reproduce and compare against ...
    • HPCTOOLKIT: Tools for performance analysis of optimized parallel programs 

      Adhianto, L.; Banerjee, S.; Fagan, M.; Krentel, M.; Marin, G.; (2008-10-03)
      HPCTOOLKIT is an integrated suite of tools that supports measurement, analysis, attribution, and presentation of application performance for both sequential and parallel programs. HPCTOOLKIT can pinpoint and quantify scalability bottlenecks in fully-optimized parallel programs with a measurement overhead of only a few percent. Recently, new capabilities ...
    • Hybrid Dixon Resultants 

      Chionh, Eng-Wee; Goldman, Ronald; Zhang, Ming (1998-05-13)
      Dixon [1908] describes three distinct homogeneous determinant representations for the resultant of three bivariate polynomials of bidegree(m,n). These Dixon resultants are the determinants of matrices of orders 6mn, 3mn and 2mn, and the entries of these matrices are respectively homogeneous of degrees 1, 2, and 3 in the coefficients of the original ...
    • Implementing a Static Debugger for a First-Order Functional Programming Language 

      Felleisen, Matthias; Steckler, Paul A. (2001-04)
      A static debugger assists a programmer in finding potential errors in programs. The key to a static debugger is set-based analysis (SBA). Many authors have described formulations of SBA, but leave open gaps among that theory, its implementation, and its use for a particular purpose. An implementation needs to confront these practical issues. While ...
    • Implementing linear algebra algorithms on high performance architectures 

      Aleksandrov, Lyudmil; Candev, Michael; Djidjev, Hristo N. (1997-07-25)
      In this paper we consider the data distribution and data movement issues related to the solution of the basic linear algebra problems on high performance systems. The algorithms we discuss in details are the Gauss andGauss-Jordan methods for solving a system of linear equations, the Cholesky's algorithm for LL^T-factorization, and QR-factorization ...
    • Implementing the Top-Down Close Algorithm on the TI 6200 Architecture 

      Dasgupta, Anshuman (2002-12-12)
      Partitioned register-set architectures pose a challenge to standard scheduling algorithms. To create an efficient schedule, an instruction scheduler for such an architecture must consider the location of an operand in the register file, the availability of the inter-cluster data bus, and the profitability of a inter-cluster copy instruction. This ...
    • Implicitly Heterogeneous Multi-stage Programming 

      Eckhardt, Jason; Kaiabachev, Roumen; Pašalić, Emir; Swadi, Kedar; Taha, Walid (2005-04-16)
      Previous work on semantics-based multi-stage programming (MSP) language design focused on homogeneous languages designs, where the generating and the generated languages are the same. Homogeneous designs simply add a hygienic quasi-quotation and evaluation mechanism to a base language. An apparent disadvantage of this approach is that the programmer ...
    • Improving Effective Bandwidth through Compiler Enhancement of Global and Dynamic Cache Reuse 

      Ding, Chen (2000-01-21)
      While CPU speed has been improved by a factor of 6400 over the past twenty years, memory bandwidth has increased by a factor of only 139 during the same period. Consequently, on modern machines the limited data supply simply cannot keep a CPU busy, and applications often utilize only a few percent of peak CPU performance. The hardware solution, which ...
    • Improving Memory Hierarchy Performance for Irregular Applications 

      Kennedy, Ken; Mellor-Crummey, John; Whalley, David (1999-03-10)
      The gap between CPU speed and memory speed in modern computer systems is widening as new generations of hardware are introduced. Loop blocking and prefetching transformations help bridge this gap for regular applications; however, these techniques don't deal well with irregular applications. This paper investigates using data and computation reordering ...
    • Improving Performance with Integrated Program Transformations 

      Jin, Guohua; Mellor-Crummey, John; Qasem, Apan (2004-09-09)
      Achieving a high fraction of peak performance on today’s computer systems is difficult for complex scientific applications. To do so, an application’s characteristics must be tailored to exploit the characteristics of its target architecture. Today, commercial compilers do not adequately tailor programs automatically; thus, application scientists ...
    • Improving TLB Miss Handling with Page Table Pointer Caches 

      Wu, Michael; Zwaenepoel, Willy (1997-12-16)
      Page table pointer caches are a hardware supplement for TLBs that cache pointers to pages of page table entries rather than page table entries themselves. A PTPC traps and handles most TLB misses in hardware with low overhead (usually a single memory access). PTPC misses are filled in software, allowing for an easy hardware implementation, similar ...
    • Input vector control for post-silicon leakage current minimization under manufacturing variations 

      Alkabani, Yousra; Koushanfar, Farinaz; Massey, Tammara; Potkonjak, Miodrag (2008-02-04)
      We present the first approach for post-silicon leakage power reduction through input vector control (IVC) that takes into account the impact of the manufacturing variability (MV). Because of the MV, the integrated circuits (ICs) implementing one design require different input vectors to achieve their lowest leakage states. There are two major challenges ...
    • Inside Time-based Software Transactional Memory 

      Zhang, Rui; Budimlić, Zoran; Scherer, William N., III (2007-07-06)
      We present a comprehensive analysis and experimental evaluation of time-based validation techniques for Software Transactional Memory (STM). Time-based validation techniques emerge recently as an effective way to reduce the validation overhead for STM systems. In a time-based strategy, information based on global time enables the system to avoid a ...
    • Interprocedural Pointer Analysis for C 

      Lu, John (1998-05-20)
      Many powerful code optimization techniques rely on accurate information connecting the definitions and uses of values in a program. This information is difficult to produce for programs written with pointer-based languages such as C. For values in memory locations, accurate information is difficult to obtain at call sites and pointer-based memory ...
    • Interprocedural Strength Reduction of Critical Sections in Explicitly-Parallel Programs 

      Barik, Rajkishore; Sarkar, Vivek; Zhao, Jisheng (2013-05-01)
      In this paper, we introduce novel compiler optimization techniques to reduce the number of operations performed in critical sections that occur in explicitly-parallel programs. Specifically, we focus on three code transformations: 1) Partial Strength Reduction (PSR) of critical sections to replace critical sections by non-critical sections on certain ...