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Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink
(IEEE, 2003-11-01)
In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink re-ceivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz ...