Now showing items 1-4 of 4
A General Hardware/Software Co-design Methodology for Embedded Signal Processing and Multimedia Workloads
This paper presents a hardware/software co-design methodology for partitioning real-time embedded multimedia applications between software programmable DSPs and hardware based FPGA coprocessors. By following a strict set ...
Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed
The performance of two field programmable gate array (FPGA) implementations of a linear minimum mean square error (LMMSE) based detector is evaluated in real-time radio channels. Two square root free algorithms based on ...
Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems
This paper shows how iterative hardware/software partitioning in heterogeneous DSP/FPGA based embedded systems can be utilized to achieve real-time deadlines of modern 3GPP wireless equalization workloads. By utilizing a ...
HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS
This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, ...