Now showing items 1-10 of 91
Wireless @ Wired Speeds
This is a poster from the first 100x100 project meeting. It outlines some basic concepts in MIMO algorithm and system design at a relatively high, accessible level.
Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures
Processors for mobile handsets in 3G cellular systems require: high speed, flexibility and low power dissipation. While computationally efficient, ASIC processors are often not flexible enough to support necessary ...
ASIP Architecture for Future Wireless Systems: Flexibility and Customization
Efficiency and flexibility are crucial features of the processors in the next generation of wireless cellular systems. Processors need to be efficient in order to satisfy real-time requirements for very demanding algorithms ...
Power optimization in multiple transmit antenna communication systems
We explore optimal ways of communicating (with a power constraint) over multiple antenna communication systems by managing spatial power distribution. We find that Mutual Coupling (MC), the interaction between antenna ...
Useful Facts about the Kullback-Leibler Discrimination Distance
This report contains a list of some of the more prominent properties and theorems concerning the Kullback-Leibler (KL) discrimination distance. A brief discussion is also provided indicating the type of problems in which ...
Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study
In this paper, we present an efficient LMMSE chip equalizer to suppress the interference caused by the multipath fading channel in the MIMO multi-code CDMA downlink. The block-Toeplitz structure in the correlation matrix ...
Semi-Parallel Architectures For Real-time LDPC Coding
Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close ...
Improving power efficiency in stream processors through dynamic cluster reconfiguration
Stream processors support hundreds of functional units in a programmable architecture by clustering functional units and utilizing a bandwidth hierarchy. Clusters are the dominant source of power consumption in stream ...
Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation
Emerging applications such as high definition television (HDTV), streaming video, image processing in embedded applications and signal processing in high-speed wireless communications are driving a need for high performance ...
Compact Hardware Accelerator for Functional Verification and Rapid Prototyping of 4G Wireless Communication Systems
In this paper, we propose an FPGA-based hardware accelerator platform with Xilinx Virtex-II V3000 in a compact PCMCIA form factor. By partitioning the complex algorithms in the 4G simulator to the hardware accelerator, ...