Now showing items 1-3 of 3
Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study
In this paper, we present an efficient LMMSE chip equalizer to suppress the interference caused by the multipath fading channel in the MIMO multi-code CDMA downlink. The block-Toeplitz structure in the correlation matrix ...
Compact Hardware Accelerator for Functional Verification and Rapid Prototyping of 4G Wireless Communication Systems
In this paper, we propose an FPGA-based hardware accelerator platform with Xilinx Virtex-II V3000 in a compact PCMCIA form factor. By partitioning the complex algorithms in the 4G simulator to the hardware accelerator, ...
Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems
In this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference ...