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Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures
Processors for mobile handsets in 3G cellular systems require: high speed, flexibility and low power dissipation. While computationally efficient, ASIC processors are often not flexible enough to support necessary ...
ASIP Architecture for Future Wireless Systems: Flexibility and Customization
Efficiency and flexibility are crucial features of the processors in the next generation of wireless cellular systems. Processors need to be efficient in order to satisfy real-time requirements for very demanding algorithms ...
White Paper on IEEE 802.11b Mobile Channel Modeling
Researchers from Rice Universityâ s Center for Multimedia Communications (CMC) recently conducted experiments with the goal of understanding and quantifying the effects of various channel effects on an 802.11b link. In ...
PhD Thesis LaTeX template 2008
This item contains a set of template latex files for the PhD thesis at Rice University.
Sphere detection and LDPC decoding algorithms and architectures for wireless systems
Ever increasing demand for high data rate wireless transmissions with high spectral efficiency leads to utilization of communication systems with multiple transmit and receive antennas. In addition, excellent error-rate ...
802.11b Operating in a Mobile Channel: Performance and Challenges
In the past, the worlds of wireless voice and data transmission have been largely disjoint. Voice traffic has been carried over circuit-switched cellular links, and data has been largely restricted to packet-switched ...
Architecture and Algorithm for a Stochastic Soft-output MIMO Detector
In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, ...
Channel equalization algorithms for MIMO downlink and ASIP architectures
Processors for mobile handsets in 3G cellular systems require: high speed, flexibility and low power dissipation. While computationally efficient, ASIC processors are often not flexible enough to support necessary variations ...
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices
A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the ...
Frequency-Domain ICI Estimation, Shortening, and Cancellation in OFDM Receivers
Orthogonal frequency division multiplexing (OFDM) communication systems encounter performance limitations due to time-varying channels common in wireless applications. The channel variations introduce inter-carrier ...