Now showing items 1-13 of 13

  • Accelerating Computer Vision Algorithms Using OpenCL Framework on Mobile Devices - A Case Study 

    Wang, Guohui; Xiong, Y.; Yun, Jay; Cavallaro, Joseph R. (IEEE, 2013-06)
    Recently, general-purpose computing on graphics processing units (GPGPU) has been enabled on mobile devices thanks to the emerging heterogeneous programming models such as OpenCL. The capability of GPGPU on mobile devices ...
  • A Fast and Efficient Sift Detector Using The Mobile GPU 

    Rister, Blaine; Wang, Guohui; Wu, Michael; Cavallaro, Joseph R. (IEEE, 2013-06)
    Emerging mobile applications, such as augmented reality, demand robust feature detection at high frame rates. We present an implementation of the popular Scale-Invariant Feature Transform (SIFT) feature detection algorithm ...
  • FPGA Prototyping of A High Data Rate LTE Uplink Baseband Receiver 

    Wang, Guohui; Yin, Bei; Amiri, Kiarash; Sun, Yang; Wu, Michael; Cavallaro, Joseph R. (IEEE, 2009-11-01)
    The Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard is becoming the appropriate choice to pave the way for the next generation wireless and cellular standards. While the popular OFDM ...
  • GPU Accelerated Scalable Parallel Decoding of LDPC Codes 

    Wang, Guohui; Wu, Michael; Sun, Yang (IEEE, 2011-11-01)
    This paper proposes a flexible low-density parity-check (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput. LDPC codes are widely adopted by the new emerging standards for ...
  • High-Level Design Tools for Complex DSP Applications 

    Sun, Yang; Amiri, Kiarash; Wang, Guohui; Yin, Bei; Cavallaro, Joseph R.; Ly, Tai (Elsevier, Waltham, MA, 2012-07-12)
    High-level synthesis design methodology - High level synthesis (HLS) [1], also known as behavioral synthesis and algorithmic synthesis, is a design process in which a high level, functional description of a design is ...
  • High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder 

    Wang, Guohui; Sun, Yang; Cavallaro, Joseph R.; Guo, Yuanbin (IEEE, 2011-09-01)
    To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits ...
  • Highly Scalable On-the-Fly Interleaved Address Generation for UMTS/HSPA+ Parallel Turbo Decoder 

    Vosoughi, Aida; Wang, Guohui; Shen, Hao; Cavallaro, Joseph R.; Guo, Yuanbin (24th IEEE International Conference on Application-specific Systems, Architectures and Processors, 2013-06-01)
    High throughput parallel interleaver design is a major challenge in designing parallel turbo decoders that conform to high data rate requirements of advanced standards such as HSPA+. The hardware complexity of the HSPA+ ...
  • Implementation of a High Throughput 3GPP Turbo Decoder on GPU 

    Wu, Michael; Sun, Yang; Wang, Guohui; Cavallaro, Joseph R. (Springer, 2011-11-01)
    Turbo code is a computationally intensive channel code that is widely used in current and upcoming wireless standards. General-purpose graphics processor unit (GPGPU) is a programmable commodity processor that achieves ...
  • Low Complexity Opportunistic Decoder for Network Coding 

    Yin, Bei; Wu, Michael; Wang, Guohui; Cavallaro, Joseph R. (IEEE, 2012-12-01)
    In this paper, we propose a novel opportunistic decoding scheme for network coding decoder which significantly reduces the decoder complexity and increases the throughput. Network coding was proposed to improve the ...
  • A Massively Parallel Implementation of QC-LDPC Decoder on GPU 

    Wang, Guohui; Wu, Michael; Sun, Yang; Cavallaro, Joseph R. (IEEE, 2011-06-01)
    The graphics processor unit (GPU) is able to provide a low-cost and flexible software-based multi-core architecture for high performance computing. However, it is still very challenging to efficiently map the real-world ...
  • Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes 

    Sun, Yang; Wang, Guohui; Cavallaro, Joseph R. (IEEE, 2011-05-01)
    We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity ...
  • Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder 

    Wang, Guohui; Vosoughi, Aida; Shen, Hao; Cavallaro, Joseph R.; Guo, Yuanbin (IEEE, 2013-05)
    Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel ...
  • Parallel Nonbinary LDPC Decoding on GPU 

    Wang, Guohui; Shen, Hao; Yin, Bei; Wu, Michael; Sun, Yang; Cavallaro, Joseph R. (IEEE, 2012-12-01)
    Nonbinary Low-Density Parity-Check (LDPC) codes are a class of error-correcting codes constructed over the Galois field GF(q) for q > 2. As extensions of binary LDPC codes, nonbinary LDPC codes can provide better ...