Now showing items 1-18 of 18

  • CORDIC Arithmetic for an SVD Processor 

    Cavallaro, Joseph R.; Luk, Franklin T. (The Computer Society of the IEEE, 1987-05-01)
    Arithmetic issues in the calculation of the Singular Value Decomposition (SVD) are discussed. Traditional algorithms using hardware division and square root are replaced with the special purpose CORDIC algorithms for ...
  • CORDIC Arithmetic for an SVD Processor 

    Cavallaro, Joseph R.; Luk, Franklin T. (1988-06-20)
    Arithmetic issues in the calculation of the Singular Value Decomposition (SVD) are discussed. Traditional algorithms using hardware division and square root are replaced with the special purpose CORDIC algorithms for ...
  • An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture 

    Guo, Yuanbin; Zhang, Jianzhong (Charlie); McCain, Dennis; Cavallaro, Joseph R. (2005-12-01)
    In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF x NF) with O((NF)³) complexity to some ...
  • An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture 

    Guo, Yuanbin; Zhang, Jianzhong; McCain, Dennis; Cavallaro, Joseph R. (Hindawi Publishing Corporation, 2006-02-01)
    We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size (NF×NF) with O((NF)3) complexity to some FFT operations with ...
  • Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder 

    Sun, Yang; Cavallaro, Joseph R. (Elsevier, 2011-09-01)
    We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high throughput 3GPP LTE/LTE-Advance ...
  • Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers 

    Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam (Kluwer Academic Pubishers, 2002-06-20)
    This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband processing operations in wireless base-station receivers ...
  • Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors 

    Kota, Kishore; Cavallaro, Joseph R. (1993-07-20)
    The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. It is desirable to use fixed-point CORDIC units in such systems, since ...
  • Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder 

    Wang, Guohui; Vosoughi, Aida; Shen, Hao; Cavallaro, Joseph R.; Guo, Yuanbin (IEEE, 2013-05)
    Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel ...
  • Parallel VLSI Architectures for Multi-Gbps MIMO Communication Systems 

    Sun, Yang (2011)
    In wireless communications, the use of multiple antennas at both the transmitter and the receiver is a key technology to enable high data rate transmission without additional bandwidth or transmit power. Multiple-input ...
  • Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots 

    Walker, Ian D.; Cavallaro, Joseph R. (IEEE Computer Society Press, 1993-05-01)
    We describe new architectures for the efficient computation of redundant manipulator kinematics (direct and inverse). By calculating the core of the problem in hardware, we can make full use of the redundancy by implementing ...
  • Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots 

    Walker, Ian D.; Cavallaro, Joseph R. (Kluwer Academic Publishers, 1994-01-01)
    We describe new architectures for the efficient computation of redundant manipulator kinematics (direct and inverse). By calculating the core of the problem in hardware, we can make full use of the redundancy by implementing ...
  • Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology 

    Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.; Takach, Andres (Hindawi Publishing Corporation, 2006-07-01)
    Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences ...
  • Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers 

    Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam (IEEE, 2002-07-20)
    This paper presents alogrithms and architecture designs that can meet real-time requirements of multiuser channel estimation and detection in future wireless base-station receivers. Sophisticated algorithms proposed to ...
  • Redundant and Online CORDIC for Unitary Transformations 

    Hemkumar, Nariankadu D.; Cavallaro, Joseph R. (1994-08-20)
    Two-sided unitary transformations of arbitrary 2 x 2 matrices are needed in parallel algorithms based on Jacobi-like methods for eigenvalue and singulare value decompositions of complex matrices. This paper presents a ...
  • A Systolic VLSI Architecture for Complex SVD 

    Hemkumar, Nariankadu D.; Cavallaro, Joseph R. (1992-05-20)
    A systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering" is presented. A novel two-step, two-sided unitary transformation scheme, tailored to the use of ...
  • Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture 

    Sun, Yang; Cavallaro, Joseph R. (IEEE, 2012-05-01)
    In this paper, we propose a trellis-search based soft-input soft-output detection algorithm and its very large scale integration (VLSI) architecture for iterative multiple-input multiple-output (MIMO) receivers. We construct ...
  • VLSI Implementation of a CORDIC SVD Processor 

    Cavallaro, Joseph R.; Keleher, Michael P.; Price, Russell H.; Thomas, Gregory S. (1991-06-20)
    The design and custom CMOS VLSI implementation of a CORDIC SVD processor is presented. Special-purpose parallel processor arrays have many important applications in real-time signal processing. The processor architecture ...
  • VLSI Implementation of Mallat's Fast Discrete Wavelet 

    Guo, Yuanbin; Zhang, Hongzhou; Wang, Xuguang; Cavallaro, Joseph R. (2001-11-20)
    This paper proposes a novel VLSI architecture to compute the DWT (discrete wavelet transform) coefficients using Mallat's algorithm with reduced complexity. We studied the commonality embedded in the mirror filters of the ...