Browsing George R. Brown School of Engineering by Author "Karkooti, Marjan"
Now showing items 1-14 of 14
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Configurable LDPC Decoder Architecture for Regular and Irregular Codes
(2008-11-01)Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents ... -
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
(2006-09-01)With the current trend of the increase in the data-rate requirements of wireless systems, there will be a huge need to increase their performance by utilizing more sophisticated channel coding algorithms. Low Density ... -
Distributed Decoding in Cooperative Communications
(2007-11-01)In this paper, we present a novel relaying strategy called distributed and partial decoding. This strategy can be viewed as a variation of the decode and forward with the difference that the relay partially decodes the ... -
Distributed partial decoding in cooperative communication systems
(2009)Increasing demand for wireless services is putting major pressure on network resources, which demands a new paradigm with a more efficient design. Recently, cooperative communications has emerged as a viable option for ... -
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
(2005-10-01)This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this ... -
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
(2005-11-01)This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this ... -
HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS
(2006-10-01)This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, ... -
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices
(2006-09-01)A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the ... -
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices
(2006-02-01)High throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the ... -
Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area
(2006-09-01)In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths (up to 2.5K bits), several decoder solutions with different levels of processing parallelism ... -
Semi-Parallel Architectures For Real-time LDPC Coding
(2004-05-01)Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close ... -
Semi-parallel architectures for real-time LDPC coding
(2004)Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. Low Density Parity Check codes are the best known ECC code that can achieve data rates very close ... -
Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding
(2004-04-01)This paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product ... -
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
(2007-05-01)A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose ...
