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The impact of instruction-level parallelism on multiprocessor performance and simulation methodology
Current microprocessors exploit high levels of instruction-level parallelism (ILP). This thesis presents the first detailed analysis of the impact of such processors on shared-memory multiprocessors. We find that ILP ...
Exploiting instruction-level parallelism for memory system performance
Current microprocessors improve performance by exploiting instruction-level parallelism (ILP). ILP hardware techniques such as multiple instruction issue, out-of-order (dynamic) issue, and non-blocking reads can accelerate ...