This thesis presents new techniques for simulating multiprogramming and interrupt servicing in an execution driven simulation environment. We have incorporated these techniques into the Rice Parallel Processing Testbed ...

Simple instruction set array processors are groups of regularly connected processors with small instruction sets and local memories. The processors are augmented by built-in communication instructions. Because of the ...

This thesis studies the performance of multistage interconnection networks (MINs) using execution-driven simulation. The networks were studied with varying network configurations, numbers of inputs and outputs of the network ...