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Efficient simulation of simple instruction set array processors
Simple instruction set array processors are groups of regularly connected processors with small instruction sets and local memories. The processors are augmented by built-in communication instructions. Because of the ...
Performance prediction of packet switched multistage interconnection networks in an execution-driven environment
This thesis studies the performance of multistage interconnection networks (MINs) using execution-driven simulation. The networks were studied with varying network configurations, numbers of inputs and outputs of the network ...
Modeling process scheduling and system software in multiprocessors
This thesis presents new techniques for simulating multiprogramming and interrupt servicing in an execution driven simulation environment. We have incorporated these techniques into the Rice Parallel Processing Testbed ...
Synchronization, coherence, and consistency for high performance shared memory multiprocessing
Although improved device technology has increased the performance of computer systems, fundamental hardware limitations and the need to build faster systems using existing technology have led many computer system designers ...