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dc.contributor.authorWang, Guohui
Vosoughi, Aida
Shen, Hao
Cavallaro, Joseph R.
Guo, Yuanbin
dc.date.accessioned 2013-10-25T21:20:22Z
dc.date.available 2013-10-25T21:20:22Z
dc.date.issued 2013-05
dc.identifier.citation G. Wang, A. Vosoughi, H. Shen, J. R. Cavallaro and Y. Guo, "Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder," 2013.
dc.identifier.urihttps://hdl.handle.net/1911/75012
dc.description.abstract Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel interleaving address generation hardware very difficult to implement. In this paper, we propose a parallel interleaver architecture that can generate multiple interleaving addresses on-the-fly. We devised a novel scheduling scheme with which we can use more efficient buffer structures to eliminate memory contention. The synthesis results show that the proposed architecture with the new scheduling scheme can significantly reduce memory usage and hardware complexity. The proposed architecture also shows great flexibility and scalability compared to prior work.
dc.description.sponsorship US National Science Foundation grant EECS-1232274
dc.description.sponsorship US National Science Foundation grant EECS-0925942
dc.description.sponsorship US National Science Foundation grant CNS-0923479
dc.language.iso eng
dc.publisher IEEE
dc.subjectVLSI
turbo decoder
parallel interleaver
HSPA+
high throughput
contention-free
parallel processing
memory conflict
dc.title Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder
dc.type Conference paper
dc.citation.location Beijing, China
dc.citation.conferenceName IEEE International Symposium on Circuits and Systems (ISCAS)
dc.citation.conferenceDate 2013
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1109/ISCAS.2013.6572102
dc.citation.firstpage 1340
dc.citation.lastpage 1343


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  • ECE Publications [1289]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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