Cavallaro, Joseph R.
G. Wang, A. Vosoughi, H. Shen, J. R. Cavallaro and Y. Guo, "Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder," 2013.
Parallel architecture is required for high throughput turbo
decoder to meet the data rate requirements of the emerging wireless communication
systems. However, due to the severe memory conflict problem
caused by parallel architectures, the interleaver design has become a
major challenge that limits the achievable throughput. Moreover, the high
complexity of the interleaver algorithm makes the parallel interleaving
address generation hardware very difficult to implement. In this paper,
we propose a parallel interleaver architecture that can generate multiple
interleaving addresses on-the-fly. We devised a novel scheduling scheme
with which we can use more efficient buffer structures to eliminate memory
contention. The synthesis results show that the proposed architecture
with the new scheduling scheme can significantly reduce memory usage
and hardware complexity. The proposed architecture also shows great
flexibility and scalability compared to prior work.
US National Science Foundation grant EECS-1232274
US National Science Foundation grant EECS-0925942
US National Science Foundation grant CNS-0923479
Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder
IEEE International Symposium on Circuits and Systems (ISCAS)