Rice Univesrity Logo
    • FAQ
    • Deposit your work
    • Login
    View Item 
    •   Rice Scholarship Home
    • Faculty & Staff Research
    • George R. Brown School of Engineering
    • Electrical and Computer Engineering
    • ECE Publications
    • View Item
    •   Rice Scholarship Home
    • Faculty & Staff Research
    • George R. Brown School of Engineering
    • Electrical and Computer Engineering
    • ECE Publications
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder

    Thumbnail
    Name:
    2013_ISCAS_Turbo_Wang_B4L-A3-1 ...
    Size:
    1.345Mb
    Format:
    PDF
    View/Open
    Author
    Wang, Guohui; Vosoughi, Aida; Shen, Hao; Cavallaro, Joseph R.; Guo, Yuanbin
    Date
    2013-05
    Abstract
    Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel interleaving address generation hardware very difficult to implement. In this paper, we propose a parallel interleaver architecture that can generate multiple interleaving addresses on-the-fly. We devised a novel scheduling scheme with which we can use more efficient buffer structures to eliminate memory contention. The synthesis results show that the proposed architecture with the new scheduling scheme can significantly reduce memory usage and hardware complexity. The proposed architecture also shows great flexibility and scalability compared to prior work.
    Citation
    G. Wang, A. Vosoughi, H. Shen, J. R. Cavallaro and Y. Guo, "Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder," 2013.
    Published Version
    http://dx.doi.org/10.1109/ISCAS.2013.6572102
    Keyword
    VLSI; turbo decoder; parallel interleaver; HSPA+; high throughput; More... contention-free; parallel processing; memory conflict Less...
    Type
    Conference paper
    Publisher
    IEEE
    Citable link to this page
    https://hdl.handle.net/1911/75012
    Metadata
    Show full item record
    Collections
    • ECE Publications [1443]

    Home | FAQ | Contact Us | Privacy Notice | Accessibility Statement
    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892
    Site Map

     

    Searching scope

    Browse

    Entire ArchiveCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsTypeThis CollectionBy Issue DateAuthorsTitlesSubjectsType

    My Account

    Login

    Statistics

    View Usage Statistics

    Home | FAQ | Contact Us | Privacy Notice | Accessibility Statement
    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892
    Site Map