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dc.contributor.advisor Baraniuk, Richard G.
dc.creatorLaska, Jason N.
dc.date.accessioned 2013-03-08T00:35:23Z
dc.date.available 2013-03-08T00:35:23Z
dc.date.issued 2012
dc.identifier.citation Laska, Jason N.. "Regime Change: Sampling Rate vs. Bit-Depth in Compressive Sensing." (2012) Diss., Rice University. https://hdl.handle.net/1911/70305.
dc.identifier.urihttps://hdl.handle.net/1911/70305
dc.description.abstract The compressive sensing (CS) framework aims to ease the burden on analog-to-digital converters (ADCs) by exploiting inherent structure in natural and man-made signals. It has been demonstrated that structured signals can be acquired with just a small number of linear measurements, on the order of the signal complexity. In practice, this enables lower sampling rates that can be more easily achieved by current hardware designs. The primary bottleneck that limits ADC sampling rates is quantization, i.e., higher bit-depths impose lower sampling rates. Thus, the decreased sampling rates of CS ADCs accommodate the otherwise limiting quantizer of conventional ADCs. In this thesis, we consider a different approach to CS ADC by shifting towards lower quantizer bit-depths rather than lower sampling rates. We explore the extreme case where each measurement is quantized to just one bit, representing its sign. We develop a new theoretical framework to analyze this extreme case and develop new algorithms for signal reconstruction from such coarsely quantized measurements. The 1-bit CS framework leads us to scenarios where it may be more appropriate to reduce bit-depth instead of sampling rate. We find that there exist two distinct regimes of operation that correspond to high/low signal-to-noise ratio (SNR). In the measurement compression (MC) regime, a high SNR favors acquiring fewer measurements with more bits per measurement (as in conventional CS); in the quantization compression (QC) regime, a low SNR favors acquiring more measurements with fewer bits per measurement (as in this thesis). A surprise from our analysis and experiments is that in many practical applications it is better to operate in the QC regime, even acquiring as few as 1 bit per measurement. The above philosophy extends further to practical CS ADC system designs. We propose two new CS architectures, one of which takes advantage of the fact that the sampling and quantization operations are performed by two different hardware components. The former can be employed at high rates with minimal costs while the latter cannot. Thus, we develop a system that discretizes in time, performs CS preconditioning techniques, and then quantizes at a low rate.
dc.format.extent 227 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectApplied sciences
Regime change
Sampling rate
Bit-depth
Compressive sensing
Applied mathematics
Electrical engineering
Computer science
dc.title Regime Change: Sampling Rate vs. Bit-Depth in Compressive Sensing
dc.type Thesis
dc.identifier.digital LaskaJ
dc.type.material Text
thesis.degree.department Electrical Engineering
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Doctoral
thesis.degree.name Doctor of Philosophy
dc.identifier.callno THESIS E.E. 2012 LASKA


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