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dc.contributor.advisor Varman, Peter J.
dc.creatorDu, Kai
dc.date.accessioned 2013-03-08T00:33:27Z
dc.date.available 2013-03-08T00:33:27Z
dc.date.issued 2012
dc.identifier.urihttps://hdl.handle.net/1911/70231
dc.description.abstract This thesis describes the design and the optimization of a low overhead, high performance variable latency carry select adder. Previous researchers believed that the traditional adder has reached the theoretical speed bound. However, a considerable portion of hardware resources of the traditional adder is only used in the worst case. Based on this observation, variable latency adders have been proposed to improve on the theoretical limit, but such adders incur significant area overhead. By combining previous variable latency adders with carry select addition, this work describes a novel variable latency carry select adder. Applying carry select addition in the variable latency adder design significantly reduces the area overhead and increases its performance. This variable latency adder is faster and smaller than previous variable latency adders. Furthermore, this variable latency adder can be optimized to be faster and smaller than the fastest adder generated by the Synopsys DesignWare building block IP.
dc.format.extent 62 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectApplied sciences
Electrical engineering
dc.title High Performance Reliable Variable Latency Carry Select Addition
dc.identifier.digital DuK
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Electrical and Computer Engineering
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Du, Kai. "High Performance Reliable Variable Latency Carry Select Addition." (2012) Master’s Thesis, Rice University. https://hdl.handle.net/1911/70231.


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