The emergence of lightweight embedded devices imposes stringent constraints on
the area and power of the circuits used to construct them. Meanwhile, many of
these embedded devices are used in applications that require diversity and flexibility
to make them secure and adaptable to the fluctuating workload or variable fabric.
While field programmable gate arrays (FPGAs) provide high flexibility, the use of
application specific integrated circuits (ASICs) to implement such devices is more
appealing because ASICs can currently provide an order of magnitude less area and
better performance in terms of power and speed. My proposed research introduces the
N-variant hardware design methodology that adds the sufficient flexibility needed by
such devices while preserving the performance and area advantages of using ASICs.
The N-variant hardware design embeds different variants of the design control
part on the same IC to provide diversity and flexibility. Because the control circuitry
usually represents a small fraction of the whole circuit, using multiple versions of the
control circuitry is expected to have a low overhead. The objective of my thesis is to
formulate a method that provides the following advantages: (i) ease of integration in
the current ASIC design flow, (ii) minimal impact on the performance and area of the
ASIC design, and (iii) providing a wide range of applications for hardware security
and tuning the performance of chips either statically (e.g., post-silicon optimization)
or dynamically (at runtime). This is achieved by adding diversity at two orthogonal
levels: (i) state space diversity, and (ii) scheduling diversity. State space diversity
expands the state space of the controller. Using state space diversity, we introduce
an authentication mechanism and the first active hardware metering schemes. On the
other hand, scheduling diversity is achieved by embedding different control schedules
in the same design. The scheduling diversity can be spatial, temporal, or a hybrid
of both methods. Spatial diversity is achieved by implementing multiple control
schedules that use various parts of the chip at different rates. Temporal diversity
provides variants of the controller that can operate at unequal speeds. A hybrid of
both spatial and temporal diversities can also be implemented. Scheduling diversity
is used to add the flexibility to tune the performance of the chip. An application
of the thermal management of the chip is demonstrated using scheduling diversity.
Experimental results show that the proposed method is easy to integrate in the current
ASIC flow, has a wide range of applications, and incurs low overhead.