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dc.contributor.authorWang, Guohui
Sun, Yang
Cavallaro, Joseph R.
Guo, Yuanbin
dc.date.accessioned 2012-06-28T16:09:26Z
dc.date.available 2012-06-28T16:09:26Z
dc.date.issued 2011-09-01
dc.identifier.otherhttp://scholar.google.com/scholar?cluster=6777021284623106221&hl=en&as_sdt=0,44
dc.identifier.urihttp://hdl.handle.net/1911/64349
dc.description.abstract To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits the achievable throughput in the parallel decoders due to the massive memory conflicts. In this paper, we propose a flexible Double-Buffer based Contention-Free (DBCF) interleaver architecture that can efficiently solve the memory conflict problem for parallel turbo decoders with very high parallelism. The proposed DBCF architecture enables high throughput concurrent interleaving for multi-standard turbo decoders that support UMTS/HSPA+, LTE and WiMAX, with small datapath delays and low hardware cost. We implemented the DBCF interleaver with a 65nm CMOS technology. The implementation of this highly efficient DBCF interleaver architecture shows significant improvement in terms of the maximum throughput and occupied chip area compared to the previous work.
dc.description.sponsorship Huawei
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.publisher IEEE
dc.subjectParallel turbo decoder
Interleaver
Contention-free
UMTS
HSPA+
LTE
WiMAX
Multi-standard
dc.title High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder
dc.type Conference paper
dc.contributor.org Center for Multimedia Communication
dc.citation.pageNumber 113-121
dc.citation.location Santa Monica, CA
dc.citation.conferenceName IEEE International Conference on Application-specific System, Architectures and Processors (ASAP)
dc.citation.conferenceDate 2011
dc.type.dcmi Text
dc.identifier.citation G. Wang, Y. Sun, J. R. Cavallaro and Y. Guo, "High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder," pp. 113-121, 2011.


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  • ECE Publications [1063]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275]
    Publications by Rice Faculty and graduate students in multimedia communications

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