Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations
Cavallaro, Joseph R.
Tittel, Frank K.
Wilson, William L. Jr.
This paper describes a CAD tool (An Integrated CAD Framework) which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. The designer can modify the original layout based upon this analysis to create compact circuits with better yield capabilities. The objective of this project is to improve the manufacturability of high density VLSI integrated circuits.