Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems
Brogioli, Michael C.
Cavallaro, Joseph R.
This paper shows how iterative hardware/software partitioning in heterogeneous DSP/FPGA based embedded systems can be utilized to achieve real-time deadlines of modern 3GPP wireless equalization workloads. By utilizing a well defined set of application partitioning criteria in tandem with SOC simulation tools, we are able to show a greater than six fold improvement in application performance and ultimately meet, and even exceed real-time data processing deadlines.
MetadataShow full item record
Showing items related by title, author, creator and subject.
In search of optimal human-expert system explanations: Empirical studies of human-human and human-expert system interactions Halgren, Shannon Lee (1993)In this project explanations were studied along a continuum ranging from human-human interactions to human-expert system interactions with the goal of identifying features of successful expert system explanations. The ...
Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R. (2004-05-01)In this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference ...