Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed
Cavallaro, Joseph R.
The performance of two field programmable gate array (FPGA) implementations of a linear minimum mean square error (LMMSE) based detector is evaluated in real-time radio channels. Two square root free algorithms based on the QR decomposition (QRD) via Givens rotations, namely coordinate rotation digital computer (CORDIC) and squared Givens rotation (SGR) algorithms, are applied for the LMMSE detector implementation with pipelined systolic array architectures. The implementations are mapped to Elektrobit 2 x 2 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) hardware testbed for 4G MIMO systems (EB4G). The presented measurement results are done with a Propsim C8 MIMO channel emulator and compared to the simulated results.
FPGA; LMMSE; Pipelined systolic array architecture; MIMO-OFDM