Show simple item record

dc.contributor.authorWang, Guohui
Wu, Michael
Sun, Yang
Cavallaro, Joseph R.
dc.date.accessioned 2012-06-06T20:59:03Z
dc.date.available 2012-06-06T20:59:03Z
dc.date.issued 2011-06-01
dc.identifier.citation G. Wang, M. Wu, Y. Sun and J. R. Cavallaro, "A Massively Parallel Implementation of QC-LDPC Decoder on GPU," 2011.
dc.identifier.otherhttp://scholar.google.com/scholar?cluster=16007718846675224041&hl=en&as_sdt=0,44&as_vis=1
dc.identifier.other 10.1109/SASP.2011.5941084
dc.identifier.urihttps://hdl.handle.net/1911/64229
dc.description.abstract The graphics processor unit (GPU) is able to provide a low-cost and flexible software-based multi-core architecture for high performance computing. However, it is still very challenging to efficiently map the real-world applications to GPU and fully utilize the computational power of GPU. As a case study, we present a GPU-based implementation of a real-world digital signal processing (DSP) application: low-density parity-check (LDPC) decoder. The paper shows the efforts we made to map the algorithm onto the massively parallel architecture of GPU and fully utilize GPU’s computational resources to significantly boost the performance. Moreover, several efficient data structures have been proposed to reduce the memory access latency and the memory bandwidth requirement. Experimental results show that the proposed GPU-based LDPC decoding accelerator can take advantage of the multi-core computational power provided by GPU and achieve high throughput up to 100.3Mbps.
dc.description.sponsorship Renesas Mobile
dc.description.sponsorship Texas Instruments
dc.description.sponsorship Xilinx
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.publisher IEEE
dc.subjectGPU
Parallel computing
CUDA
LDPC decoder
dc.title A Massively Parallel Implementation of QC-LDPC Decoder on GPU
dc.type Conference paper
dc.contributor.org Center for Multimedia Communication
dc.citation.location San Diego, CA
dc.citation.conferenceName IEEE 9th Symposium on Application Specific Processors (SASP)
dc.citation.conferenceDate 2011
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1109/SASP.2011.5941084
dc.citation.firstpage 82
dc.citation.lastpage 85


Files in this item

Thumbnail

This item appears in the following Collection(s)

  • CMC Publications [268]
    Publications by Rice Faculty and graduate students in multimedia communications
  • ECE Publications [1289]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

Show simple item record