A Massively Parallel Implementation of QC-LDPC Decoder on GPU

Files in this item

Files Size Format View
2011_SASP_Wang.pdf 1.288Mb application/pdf Thumbnail

Show full item record

Item Metadata

Title: A Massively Parallel Implementation of QC-LDPC Decoder on GPU
Author: Wang, Guohui; Wu, Michael; Sun, Yang; Cavallaro, Joseph R.
Type: Conference paper
Publisher: IEEE
Citation: G. Wang, M. Wu, Y. Sun and J. R. Cavallaro, "A Massively Parallel Implementation of QC-LDPC Decoder on GPU," pp. 82-85, 2011.
Abstract: The graphics processor unit (GPU) is able to provide a low-cost and flexible software-based multi-core architecture for high performance computing. However, it is still very challenging to efficiently map the real-world applications to GPU and fully utilize the computational power of GPU. As a case study, we present a GPU-based implementation of a real-world digital signal processing (DSP) application: low-density parity-check (LDPC) decoder. The paper shows the efforts we made to map the algorithm onto the massively parallel architecture of GPU and fully utilize GPU’s computational resources to significantly boost the performance. Moreover, several efficient data structures have been proposed to reduce the memory access latency and the memory bandwidth requirement. Experimental results show that the proposed GPU-based LDPC decoding accelerator can take advantage of the multi-core computational power provided by GPU and achieve high throughput up to 100.3Mbps.
Date Published: 2011-06-01

This item appears in the following Collection(s)

  • ECE Publications [1054 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications