The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for
architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. The key phases in multi-standard system design and prototyping
include: Algorithm Mapping to Parallel Architectures – based on the real-time data and sampling rate and the resulting area, time and power complexity; Configurable Mappings and Design Exploration – based on heterogeneous architectures consisting of DSP, programmable application-specific instruction (ASIP) processors, and co-processors; and Verification and Testbed Integration
– based on prototype implementation on programmable devices and integration with RF units.
Nokia Foundation Fellowship
National Science Foundation
Rapid prototyping Application-specific architectures Reconfigurable computing Digital baseband processing
VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems
Center for Multimedia Communication
International Workshop on Convergent Technologies (IWCT)
J. R. Cavallaro, "VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems," 2005.