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dc.contributor.authorKarkooti, Marjan
Radosavljevic, Predrag
Cavallaro, Joseph R. 2012-06-04T19:21:08Z 2012-06-04T19:21:08Z 2008-11-01
dc.identifier.citation M. Karkooti, P. Radosavljevic and J. R. Cavallaro, "Configurable LDPC Decoder Architecture for Regular and Irregular Codes," Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 53, no. 1-2, 2008.
dc.description.abstract Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.
dc.description.sponsorship Nokia
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.publisher Springer
dc.subjectLow density parity check codes
Reconfigurable architectures
Error correcting codes
dc.title Configurable LDPC Decoder Architecture for Regular and Irregular Codes
dc.type Journal article
dc.citation.journalTitle Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology Center for Multimedia Communication
dc.citation.volumeNumber 53
dc.citation.issueNumber 1-2
dc.type.dcmi Text
dc.type.dcmi Text
dc.citation.firstpage 73
dc.citation.lastpage 88

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  • CMC Publications [268]
    Publications by Rice Faculty and graduate students in multimedia communications
  • ECE Publications [1225]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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