Show simple item record

dc.contributor.authorSun, Yang
Cavallaro, Joseph R. 2012-06-01T21:27:31Z 2012-06-01T21:27:31Z 2011-07-01
dc.identifier.citation Y. Sun and J. R. Cavallaro, "A Flexible LDPC/Turbo Decoder Architecture," Journal of Signal Processing Systems, vol. 64, 2011.
dc.description.abstract Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm2. The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.
dc.description.sponsorship Nokia
dc.description.sponsorship Nokia Siemens Networks (NSN)
dc.description.sponsorship Xilinx
dc.description.sponsorship Texas Instruments
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.publisher Springer
dc.subjectSISO decoder
LDPC decoder
Turbo decoder
Error correcting codes
MAP algorithm
Reconfigurable architecture
dc.title A Flexible LDPC/Turbo Decoder Architecture
dc.type Journal article
dc.citation.journalTitle Journal of Signal Processing Systems Center for Multimedia Communication
dc.citation.volumeNumber 64
dc.type.dcmi Text
dc.type.dcmi Text
dc.citation.firstpage 1
dc.citation.lastpage 16

Files in this item


This item appears in the following Collection(s)

  • ECE Publications [1401]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • Rice Wireless [268]
    Publications by Rice Faculty and graduate students in the Rice Wireless group

Show simple item record