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    Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

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    Author
    Sun, Yang; Cavallaro, Joseph R.
    Date
    2011-09-01
    Abstract
    We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are placed an routed in a 65-nm CMOS technology with a core area of 8.3mm2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations.
    Citation
    Y. Sun and J. R. Cavallaro, "Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder," Integration, the VLSI Journal, vol. 44, no. 4, 2011.
    Published Version
    http://dx.doi.org/10.1016/j.vlsi.2010.07.001
    Keyword
    QPP interleaver; Quadratic permutation polynomial; Turbo decoder; MAP decoder; VLSI; More... ASIC; 3GPP LTE Less...
    Type
    Journal article
    Publisher
    Elsevier
    Citable link to this page
    https://hdl.handle.net/1911/64200
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    • ECE Publications [1443]
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    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
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    Site Map