Show simple item record

dc.contributor.authorSengupta, Chaitali
Cavallaro, Joseph R.
Wilson, William L.
Tittel, Frank K. 2012-05-30T18:11:34Z 2012-05-30T18:11:34Z 1997-11-01
dc.description.abstract In this paper, we address the problem of identifying and evaluating “critical features” in an integrated circuit (IC) layout. The “critical features” (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying “critical features” in a layout and then evaluate the “critical features” using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (an Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates “critical features”
dc.language.iso eng
dc.publisher IEEE
dc.subjectCritical features
Process simulation
dc.title Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations
dc.type Journal article
dc.citation.journalTitle IEEE Transactions on Semiconductor Manufacturing Center for Multimedia Communication
dc.citation.volumeNumber 10
dc.citation.issueNumber 4
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doi 10.1109/66.641490
dc.citation.firstpage 482
dc.citation.lastpage 494
dc.identifier.citation C. Sengupta, J. R. Cavallaro, W. L. Wilson and F. K. Tittel, "Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 4, 1997.

Files in this item


This item appears in the following Collection(s)

  • ECE Publications [1089]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [268]
    Publications by Rice Faculty and graduate students in multimedia communications

Show simple item record