Rice Univesrity Logo
    • FAQ
    • Deposit your work
    • Login
    View Item 
    •   Rice Scholarship Home
    • Faculty & Staff Research
    • George R. Brown School of Engineering
    • Electrical and Computer Engineering
    • ECE Publications
    • View Item
    •   Rice Scholarship Home
    • Faculty & Staff Research
    • George R. Brown School of Engineering
    • Electrical and Computer Engineering
    • ECE Publications
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations

    Thumbnail
    Name:
    97ieee_trans_semi[1].pdf
    Size:
    1.203Mb
    Format:
    PDF
    View/Open
    Author
    Sengupta, Chaitali; Cavallaro, Joseph R.; Wilson, William L.; Tittel, Frank K.
    Date
    1997-11-01
    Abstract
    In this paper, we address the problem of identifying and evaluating “critical features” in an integrated circuit (IC) layout. The “critical features” (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying “critical features” in a layout and then evaluate the “critical features” using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (an Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates “critical features”
    Citation
    C. Sengupta, J. R. Cavallaro, W. L. Wilson and F. K. Tittel, "Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 4, 1997.
    Published Version
    http://dx.doi.org/10.1109/66.641490
    Keyword
    Critical features; Photolithography; Process simulation
    Type
    Journal article
    Publisher
    IEEE
    Citable link to this page
    https://hdl.handle.net/1911/64196
    Metadata
    Show full item record
    Collections
    • ECE Publications [1494]
    • Rice Wireless [268]

    Home | FAQ | Contact Us | Privacy Notice | Accessibility Statement
    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892
    Site Map

     

    Searching scope

    Browse

    Entire ArchiveCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsTypeThis CollectionBy Issue DateAuthorsTitlesSubjectsType

    My Account

    Login

    Statistics

    View Usage Statistics

    Home | FAQ | Contact Us | Privacy Notice | Accessibility Statement
    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892
    Site Map