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    Fault-Tolerant VLSI Processor Array for the SVD

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    Author
    Cavallaro, Joseph R.; Near, Christopher D.; Uyar, M. Umit
    Date
    1989-10-01
    Abstract
    Dynamic reconfiguration techniques are presented for a two-dimensional systolic array for the SVD of a matrix. Extra computation time is not required, since idle time inherent in the array is exploited. The scheme does not require additional spare processors and is easily implemented in VLSI. Only minor hardware and communication time increases within each processing element are required.
    Citation
    J. R. Cavallaro, C. D. Near and M. U. Uyar, "Fault-Tolerant VLSI Processor Array for the SVD," 1989.
    Published Version
    http://dx.doi.org/10.1109/ICCD.1989.63351
    Type
    Conference paper
    Publisher
    IEEE Computer Society Press
    Citable link to this page
    https://hdl.handle.net/1911/64164
    Metadata
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    • ECE Publications [1443]
    • Rice Wireless [268]

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    Managed by the Digital Scholarship Services at Fondren Library, Rice University
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