Now showing items 1-5 of 5

  • A Flexible LDPC/Turbo Decoder Architecture 

    Sun, Yang; Cavallaro, Joseph R. (Springer, 2011-07-01)
    Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC ...
  • A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS 

    Sun, Yang; Cavallaro, Joseph R. (IEEE, 2008-09-01)
    In this paper we present an efficient system-on-chip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable data path and can be dynamically reconfigured to support ...
  • A Massively Parallel Implementation of QC-LDPC Decoder on GPU 

    Wang, Guohui; Wu, Michael; Sun, Yang; Cavallaro, Joseph R. (IEEE, 2011-06-01)
    The graphics processor unit (GPU) is able to provide a low-cost and flexible software-based multi-core architecture for high performance computing. However, it is still very challenging to efficiently map the real-world ...
  • Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes 

    Sun, Yang; Wang, Guohui; Cavallaro, Joseph R. (IEEE, 2011-05-01)
    We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity ...
  • Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis 

    Sun, Yang; Cavallaro, Joseph R.; Ly, Tai (IEEE, 2009-09-01)
    This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool ...