Now showing items 247-266 of 268

  • Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs 

    Rajagopal, Sridhar; Jones, Bryan Allen; Cavallaro, Joseph R. (2000-10-20)
    This paper presents a multiprocessor solution to meet real-time requirements of implementing advanced algorithms for multiuser channel estimation and detection for third and fourth generation wireless base-station receivers. ...
  • Testing on the Curve: Nonlinear Analytical Redundancy for Fault Detection 

    Leuschen, Martin L.; Cavallaro, Joseph R.; Walker, Ian D. (2001-03-01)
    One of the most important areas in the robotics industry is the development of robots capable of working in hazardous environments. Providing a high level of functionality in these arenas is important simply because humans ...
  • Time-Selective Signaling and Reception for Communication over Multipath Fading Channels 

    Bhashyam, Srikrishna; Sayeed, Akbar M.; Aazhang, Behnaam (2000-01-20)
    The mobile wireless channel affords inherent diversity to combat the effects of fading. Existing code division multiple access (CDMA) systems, by virtue of spread-spectrum signaling and RAKE reception, exploit only part ...
  • Toward an Improved Understanding of Network Traffic Dynamics 

    Riedi, Rudolf H.; Willinger, Walter (2000-01-15)
    Since the discovery of long range dependence in Ethernet LAN traces there has been significant progress in developing appropriate mathematical and statistical techniques that provide a physical-based, networking-related ...
  • Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture 

    Sun, Yang; Cavallaro, Joseph R. (2012-05-01)
    In this paper, we propose a trellis-search based soft-input soft-output detection algorithm and its very large scale integration (VLSI) architecture for iterative multiple-input multiple-output (MIMO) receivers. We construct ...
  • Truncated on-line arithmetic with applications to communication systems 

    Rajagopal, Sridhar; Cavallaro, Joseph R. (2006-09-01)
    Truncation and saturation in digit-precision are very important and common operations in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use ...
  • Truncated Online Arithmetic with Applications to Communication Systems 

    Rajagopal, Sridhar; Cavallaro, Joseph R. (2006-10)
    Truncation in digit-precision is a very important and common operation in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of online ...
  • Ultrahigh Resolution Lithography with Excimer Lasers 

    Tittel, Frank K.; Erdelyi, Miklos; Sengupta, Chaitali; Bor, Zsolt; Szabo, Gabor; Cavallaro, Joseph R.; Smayling, Michael C.; Wilson, William L. (1995-07-01)
    The photolithography process is central to integrated circuit fabrication. Through this process an integrated circuit is patterned by imaging a photomask onto a layer of photoresist. The light source currently being used ...
  • UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES 

    Sun, Yang; Cavallaro, Joseph R. (2008-10-01)
    Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code structures ...
  • Untimed-C based SoC Architecture Design Space Exploration for 3G and Beyond Wireless Systems 

    Guo, Yuanbin; McCain, Dennis (2005-02-01)
    In this paper, we propose an un-timed C/C++ level verification methodology that integrates key technologies for truly high-level VLSI modelling to keep pace with the explosive complexity of SoC designs in the 3G and beyond ...
  • The Use of Fault Trees for the Design of Robots for Hazardous Environments 

    Walker, Ian D.; Cavallaro, Joseph R. (1996-01-01)
    This paper addresses the application of fault trees to the analysis of robot manipulator reliability and fault tolerance. Although a common and useful tool in other applications, fault trees have only recently been applied ...
  • Using Predictable Observer Mobility for Power Efficient Design of Sensor Networks 

    Chakrabarti, Arnab; Sabharwal, Ashutosh; Aazhang, Behnaam (2003-04-20)
    In this paper, we explore a novel avenue of saving power in sensor networks based on predictable mobility of the observer (or data sink). Predictable mobility is a good model for public transportation ve- hicles (buses, ...
  • VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems 

    Cavallaro, Joseph R. (2005-06-01)
    The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging ...
  • VLSI Architectures for Multitier Wireless Systems 

    Cavallaro, Joseph R. (1999-11-20)
    Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENÃ ) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home ...
  • VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes 

    Sun, Yang; Karkooti, Marjan; Cavallaro, Joseph R. (2007-05-01)
    A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose ...
  • VLSI implementation of the multistage detector for next generation wideband CDMA receivers 

    Xu, Gang; Rajagopal, Sridhar; Cavallaro, Joseph R.; Aazhang, Behnaam (2002-03-20)
    The multistage detection algorithm has been proposed as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time ...
  • W-CDMA real-time algorithm implementation and evaluation 

    Jones, Bryan Allen (2000-05-20)
    This paper describes a platform to enable and explore the design and implementation of next-generation CDMA wireless base stations. A DSP and FPGA-based multiprocessor board is integrated into a Simulink-based wireless ...
  • WARP, a Modular Testbed for Configurable Wireless Network Research at Rice 

    Amiri, Kiarash; Sun, Yang; Murphy, Patrick; Hunter, Chris; Cavallaro, Joseph R.; Sabharwal, Ashutosh (2007-03-01)
    Wireless Open-Access Research Platform (WARP), developed at CMC lab, Rice University, provides a scalable and configurable platform for wireless network research. Its programmability and flexibility makes it easy to prototype ...
  • WARP, a UnifiedWireless Network Testbed for Education and Research 

    Amiri, Kiarash; Sun, Yang; Murphy, Patrick; Hunter, Chris; Cavallaro, Joseph R.; Sabharwal, Ashutosh (2007-06-01)
    In this paper, we introduce the Wireless Open-Access Research Platform (WARP) developed at CMC lab, Rice University. WARP provides a scalable and configurable platform mainly designed to prototype wireless communication ...
  • What's Next for Microelectronics Education - Editorial 

    Feinsmith, Jason; Aylor, James H.; Hodson, Robert; Courtois, Bernard; Cavallaro, Joseph R.; Hines, John; Pina, Cesar; Smith, Michael; Bouldin, Don (1997-12-01)
    With funding for services like MOSIS shrinking and industry demanding more diverse skills, the microelectronics education infrastructure—indeed that of engineering education in general—is under intense pressure to change. ...