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    An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators

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    Author
    Sengupta, Chaitali
    Date
    1995-05-20
    Abstract
    This thesis presents an Integrated CAD Framework which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. This will help designers to design more compact circuits, as they will be able to see the effect on manufactured silicon. The Framework identifies areas in a layout (in Magic or CIF format) that are more prone to problemsmask for a particular set of process parameters. The designer can modify the original layout based arising out of the photolithographic process. It then creates the corresponding in-puts for closer analysis with a process simulator (Depict) and analyzes the simulator outputs to decide whether the printed layout will match the designed upon this analysis. The Framework has been used to evaluate layouts for various process techniques. These evaluations illustrate the use of the Framework in determining the limits of any lithographic process.
    Description
    Masters Thesis
    Citation
    C. Sengupta, "An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators," Masters Thesis, 1995.
    Keyword
    Integrated CAD Framework; VLSI editors; process simulators; Integrated CAD Framework; VLSI editors; More... process simulators Less...
    Type
    Thesis
    Citable link to this page
    https://hdl.handle.net/1911/20362
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    • ECE Publications [1468]
    • Rice Wireless [268]

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    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
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    Site Map