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dc.contributor.authorRixner, Scott
Dally, William J.
Kapasi, Ujval J.
Mattson, Peter
Owens, John D.
dc.creatorRixner, Scott
Dally, William J.
Kapasi, Ujval J.
Mattson, Peter
Owens, John D.
dc.date.accessioned 2007-10-31T01:01:40Z
dc.date.available 2007-10-31T01:01:40Z
dc.date.issued 2000-06-20
dc.date.submitted 2000-06-20
dc.identifier.urihttps://hdl.handle.net/1911/20279
dc.description Conference Paper
dc.description.abstract The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the "3-D" structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.
dc.language.iso eng
dc.subjectmemory system architecture
DRAM organization
media processing
dc.title Memory Access Scheduling
dc.type Conference paper
dc.date.note 2002-03-28
dc.citation.bibtexName inproceedings
dc.date.modified 2002-03-28
dc.subject.keywordmemory system architecture
DRAM organization
media processing
dc.citation.location Vancouver, B.C., Canada
dc.citation.conferenceName International Symposium on Computer Architecture (ISCA)
dc.type.dcmi Text
dc.type.dcmi Text
dc.citation.firstpage 128
dc.citation.lastpage 138
dc.identifier.citation S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson and J. D. Owens, "Memory Access Scheduling," 2000.


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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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