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dc.contributor.authorRajagopal, Sridhar
Cavallaro, Joseph R.
dc.creatorRajagopal, Sridhar
Cavallaro, Joseph R.
dc.date.accessioned 2007-10-31T00:59:45Z
dc.date.available 2007-10-31T00:59:45Z
dc.date.issued 2006-09-01
dc.date.submitted 2004-03-21
dc.identifier.citation S. Rajagopal and J. R. Cavallaro, "Truncated on-line arithmetic with applications to communication systems," IEEE Transactions on Computers, vol. 55, no. 10, 2006.
dc.identifier.urihttps://hdl.handle.net/1911/20238
dc.description Journal Paper
dc.description.abstract Truncation and saturation in digit-precision are very important and common operations in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of on-line arithmetic to provide truncated computations with communication systems as one of the applications. In contrast to truncation in conventional arithmetic, on-line arithmetic can truncate dynamically and produce both area and time benefits due to the digit-serial nature of computations. This is of great advantage in communication systems where the precision requirements can change dynamically with the environment. While truncation in conventional arithmetic can have significant truncation errors, the redundancy and most significant digit first nature of on-line arithmetic produces truncation error only in the least significant digit of the truncated result. As an application that uses significant truncation in precision, a code matched filter detector for wireless systems is designed using truncated on-line arithmetic. The detector can provide both hard decisions and soft(er) decisions dynamically as well as interface with other conventional arithmetic circuits or act as a DSP co-processor. Thus, optimized communication receivers with co-existing conventional arithmetic for saturation and on-line arithmetic for truncation can now be built. The truncated on-line arithmetic detector was also verified with a VLSI implementation in an AMI 0.5 micron MOSIS Tiny Chip process and is currently under fabrication.
dc.description.sponsorship Nokia/Texas Instruments
dc.language.iso eng
dc.subjectDynamic truncation
finite precision
on-line arithmetic
communication systems.
dc.title Truncated on-line arithmetic with applications to communication systems
dc.type Journal article
dc.citation.bibtexName article
dc.citation.journalTitle IEEE Transactions on Computers
dc.date.modified 2006-09-23
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordDynamic truncation
finite precision
on-line arithmetic
communication systems.
dc.citation.volumeNumber 55
dc.citation.issueNumber 10
dc.citation.location Houston TX
dc.relation.projecthttp://www.ece.rice.edu/~sridhar
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1109/TC.2006.168
dc.citation.firstpage 1240
dc.citation.lastpage 1252


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    Publications by Rice Faculty and graduate students in multimedia communications
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    Publications by Rice Faculty and graduate students in digital signal processing.
  • ECE Publications [1321]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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