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dc.contributor.authorRajagopal, Sridhar
Cavallaro, Joseph R.
Rixner, Scott
dc.creatorRajagopal, Sridhar
Cavallaro, Joseph R.
Rixner, Scott
dc.date.accessioned 2007-10-31T00:59:40Z
dc.date.available 2007-10-31T00:59:40Z
dc.date.issued 2004-07-01
dc.date.submitted 2004-03-21
dc.identifier.urihttp://hdl.handle.net/1911/20236
dc.description Journal Paper
dc.description.abstract We present a design framework for rapidly exploring the design space for stream processors in real-time embedded systems. Stream processors enable hundreds of arithmetic units in programmable pro-cessors by using clusters of functional units. However, to meet a certain real-time requirement for an embedded system, there is a trade-off between the number of arithmetic units in a cluster, number of clusters and the clock frequency as each solution meets real-time with a different power consumption. We have developed a design exploration tool that explores this trade-off and presents a heuristic that minimizes the power consumption in the (functional units, clusters, frequency) design space. Our design methodology relates the instruction level parallelism, subword parallelism and data parallelism to the organization of the functional units in an embedded stream processor. We show that the power minimization methodology also provides insights into the functional unit utilization of the processor. The design exploration tool exploits the static nature of signal processing workloads, providing an extremely fast design space exploration and provides an initial lower bound estimate of the real-time performance of the embedded processor. A sensitivity analysis of the design tool results to the technology and modeling also enables the designer to check the robustness of the design exploration.
dc.description.sponsorship National Science Foundation
dc.description.sponsorship Nokia/Texas Instruments
dc.language.iso eng
dc.subjectdesign space exploration
wireless systems
real-time
low power
data parallelism
instruction level parallelism
stream processors
dc.title Design space exploration for real-time embedded stream processors
dc.type Journal article
dc.citation.bibtexName article
dc.citation.journalTitle IEEE Micro
dc.date.modified 2005-11-17
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keyworddesign space exploration
wireless systems
real-time
low power
data parallelism
instruction level parallelism
stream processors
dc.citation.volumeNumber 24
dc.citation.pageNumber 54-66
dc.citation.issueNumber 4
dc.relation.softwarehttp://www.ece.rice.edu/~sridhar/software.html
dc.type.dcmi Text
dc.identifier.citation S. Rajagopal, J. R. Cavallaro and S. Rixner, "Design space exploration for real-time embedded stream processors," IEEE Micro, vol. 24, no. 4, pp. 54-66, 2004.


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  • ECE Publications [1074]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275]
    Publications by Rice Faculty and graduate students in multimedia communications

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