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dc.contributor.authorXu, Gang
Rajagopal, Sridhar
Cavallaro, Joseph R.
Aazhang, Behnaam
dc.creatorXu, Gang
Rajagopal, Sridhar
Cavallaro, Joseph R.
Aazhang, Behnaam
dc.date.accessioned 2007-10-31T00:59:15Z
dc.date.available 2007-10-31T00:59:15Z
dc.date.issued 2002-03-20
dc.date.submitted 2001-09-18
dc.identifier.citation G. Xu, S. Rajagopal, J. R. Cavallaro and B. Aazhang, "VLSI implementation of the multistage detector for next generation wideband CDMA receivers," Journal of VLSI Signal Processing, vol. 30, no. 1-3, 2002.
dc.identifier.urihttps://hdl.handle.net/1911/20227
dc.description Journal Paper
dc.description.abstract The multistage detection algorithm has been proposed as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time VLSI implementation of this detection algorithm in the uplink system, where we have achieved both high performance in interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. Under the assumption of BPSK modulation, the differences between the bit estimates from consecutive stages are 0 and ±2. Bypassing the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. However, the convergence of the algorithm is dependent on the number of users, the interference and the signal to noise ratio and hence, the detection has a variable execution time. By using just two stages of the differencing detector, we achieve predictable execution time with performance equivalent to at least eight stages of the regular multistage detector. A VLSI implementation of the differencing multistage detector is built to demonstrate the computational savings and the real-time performance potential. The detector, handling up to eight users with 12-bit fixed point precision, was fabricated using a 1.2 um CMOS technology and can process 190 Kbps/user for 8 users.
dc.description.sponsorship Texas Advanced Technology Program
dc.description.sponsorship Nokia
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.publisher Kluwer Academic Publishers
dc.subjectCDMA
multiuser detection
multistage detector
inteference cancellation
real-time implementation
dc.title VLSI implementation of the multistage detector for next generation wideband CDMA receivers
dc.type Journal article
dc.citation.bibtexName article
dc.citation.journalTitle Journal of VLSI Signal Processing
dc.date.modified 2003-11-09
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordCDMA
multiuser detection
multistage detector
inteference cancellation
real-time implementation
dc.citation.volumeNumber 30
dc.citation.issueNumber 1-3
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1023/A:1014086523082
dc.citation.firstpage 21
dc.citation.lastpage 33


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  • CMC Publications [268]
    Publications by Rice Faculty and graduate students in multimedia communications
  • ECE Publications [1289]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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