Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs
Jones, Bryan Allen
Cavallaro, Joseph R.
multiprocessor; DSPs; FPGAs; receiver algorithms; task partitioning
This paper presents a multiprocessor solution to meet real-time requirements of implementing advanced algorithms for multiuser channel estimation and detection for third and fourth generation wireless base-station receivers. We identify the key bottlenecks in the algorithms and task-partition the algorithms on multiple processors. We get speedups, ranging from 1.19X to 5.92X for a dual-DSP implementation due to both additional computational power and additional internal memory compared to a single DSP implementation using external memory. We also identify parts of the algorithm that exhibit bit-level parallelism, not utilized by DSPs. FPGAs can then be used to accelerate these parts and meet real-time requirements of 128 Kbps for next generation wireless systems.