Show simple item record

dc.contributor.authorRajagopal, Sridhar
Bhashyam, Srikrishna
Cavallaro, Joseph R.
Aazhang, Behnaam
dc.creatorRajagopal, Sridhar
Bhashyam, Srikrishna
Cavallaro, Joseph R.
Aazhang, Behnaam
dc.date.accessioned 2007-10-31T00:58:51Z
dc.date.available 2007-10-31T00:58:51Z
dc.date.issued 2000-07-20
dc.date.submitted 2000-07-20
dc.identifier.citation S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," 2000.
dc.identifier.urihttps://hdl.handle.net/1911/20218
dc.description Conference Paper
dc.description.abstract A real-time VLSI architecture is designed for multiuser channel estimation, one of the core base-band processing operations in wireless base-station receivers. Future wireless basestation receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP architectures are unable to fully exploit the parallelism and bit level arithmetic present in these algorithms. These features can be revealed and efficiently implemented by task partitioning the algorithms for a VLSI solution. We modify the channel estimation algorithm for a reduced complexity fixed-point hardware implementation. We show the complexity and hardware required for three different area-time tradeoffs: an area-constrained, a time-constrained and an area-time efficient architecture. The area-constrained architecture achieves low data rates with minimum hardware, which may be used in picocell base-stations. The time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data rates. The area-time efficient architecture meets real-time requirements with minimum area overhead. The orders-of-magnitude difference between area and time constrained solutions reveals significant inherent parallelism in the algorithm. All proposed VLSI solutions exhibit better time performance than a previous DSP implementation.
dc.description.sponsorship Texas Advanced Technology Program
dc.description.sponsorship Nokia
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.subjectVLSI architectures
baseband signal processing
wireless base-station receivers
DSP
dc.title Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers
dc.type Conference paper
dc.date.note 2001-08-18
dc.citation.bibtexName inproceedings
dc.date.modified 2003-11-10
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordVLSI architectures
baseband signal processing
wireless base-station receivers
DSP
dc.citation.conferenceName IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1109/ASAP.2000.862388
dc.citation.firstpage 173
dc.citation.lastpage 184


Files in this item

Thumbnail
Thumbnail

This item appears in the following Collection(s)

  • CMC Publications [268]
    Publications by Rice Faculty and graduate students in multimedia communications
  • DSP Publications [508]
    Publications by Rice Faculty and graduate students in digital signal processing.
  • ECE Publications [1278]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

Show simple item record