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dc.contributor.authorRadosavljevic, Predrag
de Baynast, Alexandre
Karkooti, Marjan
Cavallaro, Joseph R.
dc.creatorRadosavljevic, Predrag
de Baynast, Alexandre
Karkooti, Marjan
Cavallaro, Joseph R.
dc.date.accessioned 2007-10-31T00:58:33Z
dc.date.available 2007-10-31T00:58:33Z
dc.date.issued 2006-09-01
dc.date.submitted 2006-09-01
dc.identifier.urihttps://hdl.handle.net/1911/20212
dc.description Conference Paper
dc.description.abstract In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths (up to 2.5K bits), several decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion:~hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine multi-rate LDPC decoder architecture with the best tradeoff in terms of area size, error-correcting performance, and decoding throughput. The prototype architecture of optimal LDPC decoder is implemented on FPGA.
dc.language.iso eng
dc.subjectLDPC codes
decoder design
tradeoff between throughput and area
block-structured codes
architecture-oriented parity-check matrices
dc.title Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area
dc.type Conference paper
dc.date.note 2006-06-02
dc.citation.bibtexName inproceedings
dc.date.modified 2006-06-02
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordLDPC codes
decoder design
tradeoff between throughput and area
block-structured codes
architecture-oriented parity-check matrices
dc.citation.conferenceName IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC)
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.citation P. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro, "Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area," 2006.


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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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