High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices
de Baynast, Alexandre
Cavallaro, Joseph R.
A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for the pre-determined set of code rates. The designed decoder achieves a data throughput of more than 1 Gb/s without sacrificing the error-correcting performance of capacity-approaching irregular block codes. The architecture is prototyped on an FPGA and synthesized for an ASIC design flow.
Citable link to this pagehttps://hdl.handle.net/1911/20211
MetadataShow full item record
- ECE Publications