High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices
de Baynast, Alexandre
Cavallaro, Joseph R.
Block-structured LDPC codes; layered belief propgation; architecture-oriented design of parity-check matrices; flexible high-throughput architecture; pipelining of horizontal layers; FPGA implementation
High throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for pre-determined set of code rates. Designed decoder achieves data throughput of approximately 1 Gb/s without sacrificing error-correcting performance of capacity-approaching irregular block codes. The prototype architecture is implemented on FPGA.
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- ECE Publications