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dc.contributor.authorRadosavljevic, Predrag
dc.creatorRadosavljevic, Predrag
dc.date.accessioned 2007-10-31T00:58:13Z
dc.date.available 2007-10-31T00:58:13Z
dc.date.issued 2004-04-01
dc.date.submitted 2004-05-14
dc.identifier.urihttps://hdl.handle.net/1911/20204
dc.description Masters Thesis
dc.description.abstract Processors for mobile handsets in 3G cellular systems require: high speed, flexibility and low power dissipation. While computationally efficient, ASIC processors are often not flexible enough to support necessary variations of implemented algorithms. On the other hand, programmable DSP processors are not optimized for a specific application and often they are not able to achieve high performance with low power dissipation. As a solution we exploit programmable architectures with possibility for customization - Application Specific Instruction set Processors (ASIPs). Channel equalization based on iterative Conjugate Gradient and Least Mean Square algorithms and several algorithmic modifications are implemented in MIMO context on the same ASIPs based on Transport Triggered Architecture. Customization of ASIPs is achieved by extending the instruction set with application-specific operations. Identical customized ASIP architecture can achieve 3GPP real-time requirements in broad range of channel environments and for different equalization algorithms with reasonable clock frequency and low power dissipation.
dc.description.sponsorship Nokia
dc.description.sponsorship Nokia/Texas Instruments
dc.language.iso eng
dc.subjectChip-level equalization
MIMO
Conjugate Gradient
ASIP
TTA
dc.title Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures
dc.type Thesis
dc.citation.bibtexName mastersthesis
dc.citation.journalTitle Masters Thesis
dc.date.modified 2004-08-30
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordChip-level equalization
MIMO
Conjugate Gradient
ASIP
TTA
dc.citation.location Houston, TX
thesis.degree.level Masters
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.citation P. Radosavljevic, "Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures," Masters Thesis, 2004.


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  • ECE Publications [1426]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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