Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures
Author
Radosavljevic, Predrag
Date
2004-04-01Abstract
Processors for mobile handsets in 3G cellular systems require:
high speed, flexibility and low power dissipation. While
computationally efficient, ASIC processors are often not flexible
enough to support necessary variations of implemented algorithms.
On the other hand, programmable DSP processors are not optimized
for a specific application and often they are not able to achieve
high performance with low power dissipation.
As a solution we exploit programmable architectures with
possibility for customization - Application Specific Instruction
set Processors (ASIPs). Channel equalization based on iterative
Conjugate Gradient and Least Mean Square algorithms and several
algorithmic modifications are implemented in MIMO context on the
same ASIPs based on Transport Triggered Architecture.
Customization of ASIPs is achieved by extending the instruction
set with application-specific operations. Identical customized
ASIP architecture can achieve 3GPP real-time requirements in broad
range of channel environments and for different equalization
algorithms with reasonable clock frequency and low power
dissipation.
Description
Masters Thesis
Citation
Keyword
Type
Thesis
Citable link to this page
https://hdl.handle.net/1911/20204Metadata
Show full item recordCollections
- ECE Publications [1468]