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dc.contributor.authorPai, Vijay S.
Ranganathan, Parthasarathy
Adve, Sarita V.
dc.creatorPai, Vijay S.
Ranganathan, Parthasarathy
Adve, Sarita V.
dc.date.accessioned 2007-10-31T00:57:15Z
dc.date.available 2007-10-31T00:57:15Z
dc.date.issued 1997-02-20
dc.date.submitted 1997-02-20
dc.identifier.urihttp://hdl.handle.net/1911/20181
dc.description Conference Paper
dc.description.abstract None
dc.language.iso eng
dc.subjectinstruction-level parallelism
shared-memory multiprocessors
performance evaluation
dc.title The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology
dc.type Conference paper
dc.date.note 2002-03-20
dc.citation.bibtexName inproceedings
dc.date.modified 2002-03-20
dc.contributor.orgCITI (http://citi.rice.edu/)
dc.subject.keywordinstruction-level parallelism
shared-memory multiprocessors
performance evaluation
dc.citation.pageNumber 72-83
dc.citation.location San Antonio, TX
dc.citation.conferenceName International Symposium on High Performance Computer Architecture (HPCA)
dc.type.dcmi Text
dc.identifier.citation V. S. Pai, P. Ranganathan and S. V. Adve, "The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," pp. 72-83, 1997.


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  • ECE Publications [1059]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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