VALID: Custom ASIC Verification and FPGA Education Platform
Cavallaro, Joseph R.
This paper describes VALID, a platform for testing student designed ASICs and for teaching the basics of FPGA design. VALID is designed to maximize ease of use from a student?s perspective while maintaining enough flexibility for its use as an FPGA development and instruction platform. This system was designed entirely by students, has been successfully manufactured and is currently being used in a number of courses at Rice.
Citable link to this pagehttps://hdl.handle.net/1911/20123
MetadataShow full item record
- ECE Publications